In order to ensure reliable operation, integrated circuits require testing. Depending upon what is required of the testing, different testing techniques are available. However, it is becoming increasingly complex to test integrated circuits and new techniques are required in order to meet new safety regulations. For example, there is an increasing demand for the deployment of so-called “in-field” test solutions for integrated circuits. Indeed, in the automotive industry, in the context of compliance with most recent standards for functional safety, such as ISO 26262, a Logic Built-In Self-Test (LBIST) mechanism is employed to provide in-field testing so as to maintain a periodical test of the logic of an integrated circuit during the life of the integrated circuit. LBIST is hardware and/or software that is built into the integrated circuit so that the integrated circuit can test its operation.
“Logic BIST: State-of-the-Art and Open Problems.” (Nan Li, Gunnar Carlsson, Elena Dubrova, Kim Petersen; CoRR abs/1503.04628 (2015)) provides a review of LBIST technology.
US patent publication no 2016/033571 discloses a method of performing root cause identification for a failure on an integrated circuit with an LBIST system. The system includes one or more channel scan paths having one or more macros associated therewith, each of the one or more channel scan paths being executed during a test cycle. The channel scan paths extend between a pseudo random pattern generator and a Multiple Input Signal Register (MISR). A processor is provided to initiate one or more of the test cycles via an LBIST controller. However, the architecture disclosed requires the integrated circuit to comprise an on-chip test processing capability in order to manage the testing of the part of the logic of the integrated circuit to be tested. As such, the on-chip test processing capability is not subject to testing and so the testing of the integrated circuit as a whole is less robust as the on-chip test processing capability remains untested as part of the LBIST.
US patent publication no. 2009/327824 also discloses a plurality of test channels extending between a pseudo random pattern generator and an MISR. A memory module is provided to store LBIST test parameters and the signatures (results). Decision logic is provided, additional to the logic to be scanned, but as with the on-chip test processing capability of US 2016/033571 the decision logic itself is not subject to testing.
Even for implementations where the scanned logic and the logic controlling the scanning take turns in scanning each other, the use of dedicated logic to conduct the testing of the logic to be scanned represents a waste of die space.